SoleOPS 3.13.0, ©2005-2018Solenovo Oy

Opintojakson toteutussuunnitelma

Group504D07/Degree Programme in Information Technology (Rovaniemi)
Study unit504D14B Digital Circuits Laboratory, 3.00 ECTS credits, 80 h
Advanced Electrical Engineering
Time of implementationSpring/2009-2010
Responsible teacherYlinampa Anssi
Other teachers
Status of implementationFinished

Description status Ready
Language of instruction English
Starting and ending dates01.09.2009 - 31.05.2010
Minimum number of participants  
Maximum number of participants  
Enrolment period14.04.2009 - 31.05.2009
Implementation method
Virtuality 0 ECTS credits
R&D integration 0 ECTS credits
Resit dates of the exam
Koulutuksen aikataulu (www-linkki)
Description language English 
Assessment criteria  
Pedagogical arrangements


laboratory work in small groups ( one or two students per group )

testing on DE2 board

written reports 

Stephen Brown: Fundamentals of digital logic with VHDL design ISBN 007-124482-4
Introduce a design flow of  digital data processing machines . Functional verification with Modelsim VHDL simulator. Synchronous state machines which are designed with VHDL , high abstraction level simulation model . VHDL synthesis program Quartus2 realises VHDL code to Boolean statements and logic schematic. Designing , verifying and programming state machine to silicon ( implement on PLD device ) . Testing system on Altera DE2 board.
virtual model functional testing , simulation of VHDL model
realisation , synthesis of simulated VHDL model
implementation , programming to silicon chip (  Cyclone2 FPGA device )
testing  on Altera DE2 board

evaluation : 0 ... 5

laboratory exercises and written raports